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Model checking
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Principles of Model checking
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Computer aided verification : Fourth international workshop : Konf. CAV '92, Montreal, Canada, 29. Juny - 1. July 1992 /
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A unified approach for timing verification and delay faut testing
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Formal equivalence checking and disign debugging
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Automatic verification methods for finite state systems : Konf. International Workshop, Grenoble, France, 12.- 14. juna. 1989 /
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Synthesis and optimization of digital circuits /
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Algorithms and parallel VLSI architectures : Konf. Proceedings of the International Workshop on Algorithms and Parallel VLSI Architectures , Abbaye des Prémontrés,Pont-aMousson, France, 10.- 16. June 1990 : Obs. Vol.A., Tutorials, 475 s.. Vol.B., Proceedings, 524 s /
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Temporal verification of reactive systems : Safety /
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Algorithmic and register-transfer level synthesis:the system architect`s workbench /
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SSADM Version 4 : The advanced practitioner's guide /
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System level hardware/software co-design : An industrial approach
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High-level VLSI synthesis /
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Correct hardware design and verification methods : IFIP WG10.2 Advanced research working conference : Konf. CHARME'93, Arles, Frances, 24.- 26. May 1993 /
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Computer-Aided verification /
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Proceedings the European conference on design automation with the European event in ASIC design : 2.diel:The user forum and AUROASIC prizes sessions : Konf. EURO ASIC '93, Paris, France, 22.- 25. Feb. 1993 : Obs. 1.zv.:, 601 s.. 2.zv.:, 274 s
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Computer Aids for VLSI design /
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DARWIN2K. An Evolutionary Approach to Automated Design for Robotics
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DARWIN2K :
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Formal verification of hardware design /
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Computer science today : Recent trends and developments /
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Electronic logic systems /
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Digital logic and computer design /
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The European conference on design automation : Konf. Brussels, Belgium, 16.- 19. March 1992
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Formal methods for VLSI design /
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Algorithms and parallel VLSI architectures : Konf. Proceedings of the International Workshop on Algorithms and Parallel VLSI Architectures , Abbaye des Prémontrés,Pont-aMousson, France, 10.- 16. June 1990 : Obs. Vol.A., Tutorials, 475 s.. Vol.B., Proceedings, 524 s /
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Automatic verification methods for finite state systems : Konf. International Workshop, Grenoble, France, 12.- 14. juna. 1989 /
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The European design and test conference : Konf. Paris, France, 28. Febr. - 3. March 1994 : Obs. Proceedings, 676 s.. User Forum, 223 s
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System level hardware/software co-design : An industrial approach
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Proceedings the European conference on design automation with the European event in ASIC design : 2.diel:The user forum and AUROASIC prizes sessions : Konf. EURO ASIC '93, Paris, France, 22.- 25. Feb. 1993 : Obs. 1.zv.:, 601 s.. 2.zv.:, 274 s
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High-level VLSI synthesis /
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The European conference on design automation : Konf. Brussels, Belgium, 16.- 19. March 1992
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Distributed operating systems. The logical design /
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Synthesis and optimization of digital circuits /
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32nd design automation conference : Proceedings 1995 : Konf. San Francisco, California, 12.- 16. June 1995
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European design & test conference : Konf. ED&TC 96, Paris, France, 11.- 14. March 1996 : Obs. Proceedings, 623 s.. User forum, 299 s
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Symbolic model checking /
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Computer Aids for VLSI design /
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SPECC : Specification language and methodology
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European design & test conference : Konf. ED&TC 97, Paris, France, 27.- 30. March 1997
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DARWIN2K. An Evolutionary Approach to Automated Design for Robotics
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Algorithmic and register-transfer level synthesis:the system architect`s workbench /
-
SSADM Version 4 : The advanced practitioner's guide /
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Principles of Model checking
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Model checking
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DARWIN2K :