Citazione Stile APA (7a Edizione)
Sutherland, S. (2017). RTL Modeling with System Verilog for Simulation and Synthesis using System Verilog for ASIC and FPGA design. Tualatin.
Citazione stile Chigago Style (17a edizione)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Sutherland HDL: Tualatin, 2017.
Citatione MLA (9a ed.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Tualatin, 2017.
Attenzione: Queste citazioni potrebbero non essere precise al 100%.