VHDL: a logic synthesis approach /
Salvato in:
| Autori principali: | , |
|---|---|
| Natura: | Libro |
| Lingua: | inglese |
| Pubblicazione: |
London :
Chapman and Hall,
1997
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| Soggetti: | |
| Tags: |
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MARC
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| 041 | 0 | |a eng | |
| 044 | |a uk | ||
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| 100 | 1 | |a Naylor, David |4 aut | |
| 245 | 1 | |a VHDL: a logic synthesis approach / |c [aut.] Naylor,David; Jones,Simon | |
| 260 | |a London : |b Chapman and Hall, |c 1997 | ||
| 300 | |a 339 s | ||
| 650 | 7 | |a počítače |2 stusub | |
| 650 | 7 | |a hardware |2 estusub | |
| 650 | 7 | |a logické členy |2 stusub | |
| 650 | 7 | |a logické obvody |2 stusub | |
| 650 | 7 | |a programovanie |2 stusub | |
| 650 | 7 | |a programovacie jazyky |2 stusub | |
| 700 | 1 | |a Jones, Simon |4 aut | |
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