VHDL: a logic synthesis approach /
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
London :
Chapman and Hall,
1997
|
| Schlagworte: | |
| Tags: |
Keine Tags, Fügen Sie das erste Tag hinzu!
|
MARC
| LEADER | 00000nam a22000003a 4500 | ||
|---|---|---|---|
| 001 | stu10430 | ||
| 005 | 20150617225621.4 | ||
| 008 | 980113s1997----uk------------------eng-d | ||
| 020 | |a 0-412-61650-5 | ||
| 040 | |a STU |b slo | ||
| 041 | 0 | |a eng | |
| 044 | |a uk | ||
| 080 | |a 681.325.06 | ||
| 080 | |a 519.682 | ||
| 080 | |a 681.32.02 |7 stu_us_auth*stu8293 | ||
| 084 | |a C5210 |2 INS | ||
| 084 | |a C6110F |2 INS | ||
| 084 | |a C6140D |2 INS | ||
| 084 | |a C7410D |2 INS | ||
| 100 | 1 | |a Naylor, David |4 aut | |
| 245 | 1 | |a VHDL: a logic synthesis approach / |c [aut.] Naylor,David; Jones,Simon | |
| 260 | |a London : |b Chapman and Hall, |c 1997 | ||
| 300 | |a 339 s | ||
| 650 | 7 | |a počítače |2 stusub | |
| 650 | 7 | |a hardware |2 estusub | |
| 650 | 7 | |a logické členy |2 stusub | |
| 650 | 7 | |a logické obvody |2 stusub | |
| 650 | 7 | |a programovanie |2 stusub | |
| 650 | 7 | |a programovacie jazyky |2 stusub | |
| 700 | 1 | |a Jones, Simon |4 aut | |
| 996 | |b I5140 |c I*5140 |l II680 |s A |a 24 |w stu10430_0001 | ||